`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/06/25 00:04:10
// Design Name: 
// Module Name: Hex_7_Seg_Top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Hex_7_Seg_Top (
    input [31:0] num,
    input clk,
    input rst,
    output [6:0] a_to_g_0,
    output [6:0] a_to_g_1,
    output [7:0] an
);

    wire [7:0] len;

    assign len[0] = num[0] | num[1] | num[2] | num[3];
    assign len[1] = num[4] | num[5] | num[6] | num[7];
    assign len[2] = num[8] | num[9] | num[10] | num[11];
    assign len[3] = num[12] | num[13] | num[14] | num[15];
    assign len[4] = num[16] | num[17] | num[18] | num[19];
    assign len[5] = num[20] | num[21] | num[22] | num[23];
    assign len[6] = num[24] | num[25] | num[26] | num[27];
    assign len[7] = num[28] | num[29] | num[30] | num[31];

    wire [7:0] lenk;

    assign lenk[0] = len[0]|len[1]|len[2]|len[3]|len[4]|len[5]|len[6]|len[7];
    assign lenk[1] = len[1]|len[2]|len[3]|len[4]|len[5]|len[6]|len[7];
    assign lenk[2] = len[2]|len[3]|len[4]|len[5]|len[6]|len[7];
    assign lenk[3] = len[3]|len[4]|len[5]|len[6]|len[7];
    assign lenk[4] = len[4]|len[5]|len[6]|len[7];
    assign lenk[5] = len[5]|len[6]|len[7];
    assign lenk[6] = len[6]|len[7];
    assign lenk[7] = len[7];


    Hex_7_Seg I_Seg1 (
        .number(num[15:0]),
        .clk(clk),
        .rst(rst),
        .len(lenk[3:0]),
        .an(an[3:0]),
        .a_to_g(a_to_g_0)
    );

    Hex_7_Seg I_Seg2 (
        .number(num[31:16]),
        .clk(clk),
        .rst(rst),
        .len(lenk[7:4]),
        .an(an[7:4]),
        .a_to_g(a_to_g_1)
    );

endmodule
